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syn_fifo
- A Verilog descr iption of a synchronous FIFO memory circuit
FIFO
- 利用Verilog实现了一个FIFO，包含几个模块文件，适合初学Verilog的朋友，含测试代码。-Verilog achieved using a FIFO, a document contains several modules, suitable for novice Verilog friends, including test code.
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
FIFO_Buffer
- Verilog的FIFO源代码，可综合，并以运用到具体工程中-Verilog source code of the FIFO can be integrated and applied to specific projects
fifo_test
- FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
parallel-fifo
- 利用Verilog语言编写的并行数据传输程序，在编译环境中编译通过。- the model of parallel data transmit which is written of verilog.
asymmetric_fifo
- 高速同步非对称FIFO,verilog 代码，很有价值的参考设计。-Asymmetric high-speed synchronous FIFO, verilog code, and very valuable reference design.
Verilog
- 简易环形FIFO的设计、简单异步串行通信接口设计等-verilog
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
fifo
- fifo 即实现数据的先进先出，是用verilog编写的 就撒开了几分-fifo hjahfjhsjeikkdnakfnakjfakjkf
fifo
- FIFO verilog controller, asyn. circuit
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
sdcard_mass_storage_controller_latest.tar
- 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
FIFO
- 速度高达130MHz 可实现高速数据采集 程序源码为Verilog-Speeds up to 130MHz for high-speed data acquisition program source code for the Verilog
TERASIC_AUDIO
- 友晶提供的Audio的IP核。这个IP核提供了Verilog的硬件部分源码和相应的HAL驱动程序。-Audio provided by Friends of Crystal' s IP core. The IP core provides a Verilog hardware part of the source and the corresponding HAL driver.
fifo
- 使用verilog语言编写的fifo程序。-Use the fifo verilog language program.
afifo
- verilog编写的异步FIFO代码，功能仿真时是正确的。-verilog code written in asynchronous FIFO, functional simulation is the right time.
sfifo
- verilog编写的同步FIFO，功能仿真完全正确，大家可以参考下。-verilog write synchronization FIFO, functional simulation completely correct, we can refer to the next.
Decoy
- 外部 FIFO 的控制 verilog语言-verilog FIFo
SC16C752B
- The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission